Ferroelectric capacitors are often used in FeRAMs. The ferroelectric capacitors are etched in one or more steps. FIG. 1 illustrates a two-step prior-art process for etching a ferroelectric capacitor. A top electrode (TE) 101 and an underlying ferroelectric layer 103 are patterned by a first etching step as shown in FIG. 1(b). An underlying bottom electrode (BE) 105 is patterned by a second etching step as shown in FIG. 1(c).
Turning to FIG. 1(a), a wafer stack 100 is illustrated. Sandwiched between the top electrode 101 and the bottom electrode 105 is the ferroelectric layer 103. The top and bottom electrodes 101, 105 are composed of a noble metal such as Platinum or Iridium. The ferroelectric layer 103 can be formed of PZT, for example. The top electrode 101, ferroelectric layer 103, and bottom electrode 105 are supported by a substrate 109.
A first Ithographic step is performed whereby a first hardmask 107, often composed of TEOS, is applied on the top electrode 101 for etching the top electrode during the first etching step. During the first etching step the exposed areas of the top electrode 101 and the ferroelectric layer 103 are etched away following the pattern of the first hardmask 107.
The thickness of the first hardmask 107 is chosen according to the selectivity between the hardmask 107 material and the material of the top electrode 101 and the ferroelectric layer 103. The hardmask 107 must be thick enough so that the top electrode and ferroelectric layer are patterned before the hardmask is etched away, exposing the top electrode. Typically, the hardmask must be thicker than the stack itself, resulting in an etching process sensitive to small changes in composition and stack thickness. If the hardmask is thick compared to the capacitor thickness, unwanted residues are easily formed on the sidewalls. These undesirable effects are common when silicon dioxide (TEOS) is used for the first hardmask 107 and Pt is used for the top electrode.
After etching the top electrode 101 and the ferroelectric layer, a second lithographic step is performed whereby a second hardmask 111 is applied over remaining portions of the first hardmask 107, top electrode 101, ferroelectric layer 103, and bottom electrode 105. FIG. 1(b) shows the stack 100 following the deposition of the second hard mask 111.
During the second etching step the exposed areas of the bottom electrode 105, and sometimes some of the substrate 109, are etched away following the pattern of the second hardmask 111. The bottom electrode 105 also includes a barrier layer which is etched along with the bottom electrode 105. FIG. 1(c) shows the stack 100 following the second etching step.
The hardmasks used for both the first and second etching steps cause unwanted residues (“fences”) clinging to the sidewalls. Moreover, the thick hardmask layers result in overly thick capacitors. The steps for depositing the hardmask layers also adds complexity to the fabrication process.
A hardmask that would allow the simplified fabrication of a relatively thin capacitor stack, with fewer undesirable residues, would be beneficial.